1. Field
The invention relates to demodulators, and particularly to a circuit for demodulating a pulse width modulated carrier signal at very high speeds.
2. Prior Art
There exist many variations of circuits which demodulate a pulse width modulated type of carrier signal. Typical of existing pulse width demodulators are those circuits which use a three stage approach. First, a capacitor is allowed to charge for a period equal to the duration of the pulse. Second, when the pulse has ended, the voltage level on the capacitor is read by a clock which is locked to the carrier. Third, after sufficient time has elapsed to allow the voltage level to be read, the capacitor is then discharged in preparation for the next pulse. The sampled voltage is filtered and becomes the demodulated signal.
At frequencies above a few megahertz (MHz), the implementation of the above demodulator is difficult if accurate demodulation is required, since the process of separately reading the voltage level on the capacitor and thereafter discharging the capacitor takes a prohibitive amount of time.